XC908AS60ACFU Motorola Semiconductor Products, XC908AS60ACFU Datasheet - Page 522

• Manufacturer Part Number: XC908AS60ACFU
• Description: MC68HC908AZ60A, MC68HC908AS60A Hcmos Microcontroller Unit Technical Data
• Manufacturer: Motorola Semiconductor Products

Byte Data Link Controller (BDLC)
Technical Data
522
programmer should set TEOD after the last IFR byte has been written
into the BDR register. After TEOD has been set and the last IFR byte
has been transmitted, the CRC byte is transmitted.
If the TMIFR1 bit is set, the BDLC will attempt to transmit the
normalization symbol followed by the byte in the BDR. After the byte
in the BDR has been loaded into the transmit shift register, a TDRE
interrupt (see
main message transmit sequence. The programmer should then load
the next byte of the IFR into the BDR for transmission. When the last
byte of the IFR has been loaded into the BDR, the programmer should
set the TEOD bit in the BDLC control register 2 (BCR2). This will
instruct the BDLC to transmit a CRC byte once the byte in the BDR is
transmitted and then transmit an EOD symbol, indicating the end of
the IFR portion of the message frame.
However, if the programmer wishes to transmit a single byte followed
by a CRC byte, the programmer should load the byte into the BDR
before the EOD symbol has been received, and then set the TMIFR1
bit. Once the TDRE interrupt occurs, the programmer should then set
the TEOD bit in the BCR2. This will result in the byte in the BDR being
the only byte transmitted before the IFR CRC byte, and no TDRE
interrupt will be generated.
If the programmer attempts to set the TMIFR1 bit immediately after
the EOD symbol has been received from the bus, the TMIFR1 bit will
remain in the reset state, and no attempt will be made to transmit an
IFR byte.
If a loss of arbitration occurs when the BDLC is transmitting any byte
of a multiple byte IFR, the BDLC will go to the loss of arbitration state,
set the appropriate flag, and cease transmission.
If the BDLC loses arbitration during the IFR, the TMIFR1 bit will be
cleared and no attempt will be made to retransmit the byte in the BDR.
If loss of arbitration occurs in the last two bits of the IFR byte, two
additional 1 bits will be sent out.
0 = The TMIFR1 bit will be cleared automatically – once the BDLC
has successfully transmitted the CRC byte and EOD
symbol – by the detection of an error on the multiplex bus or by
a transmitter underrun caused when the programmer does not
write another byte to the BDR after the TDRE interrupt.
Byte Data Link Controller (BDLC)
BDLC State Vector
Register) will occur similar to the
MC68HC908AZ60A — Rev 2.0
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