XC908AS60ACFU Motorola Semiconductor Products, XC908AS60ACFU Datasheet - Page 371

• Manufacturer Part Number: XC908AS60ACFU
• Description: MC68HC908AZ60A, MC68HC908AS60A Hcmos Microcontroller Unit Technical Data
• Manufacturer: Motorola Semiconductor Products

22.8.2 Data Direction Register F
MC68HC908AZ60A — Rev 2.0
MOTOROLA
NOTE:
NOTE:
Address:
TBCH[1:0] — Timer B Channel I/O Bits
Data direction register F (DDRF) does not affect the data direction of port
F pins that are being used by the TIM. However, the DDRF bits always
determine whether reading port F returns the states of the latches or the
states of the pins. (See
Data direction register F determines whether each port F pin is an input
or an output. Writing a logic 1 to a DDRF bit enables the output buffer for
the corresponding port F pin; a logic 0 disables the output buffer.
DDRF[6:0] — Data Direction Register F Bits
Avoid glitches on port F pins by writing to the port F data register before
changing data direction register F bits from 0 to 1.
Figure 22-19
Reset:
Read:
Write:
The PTF5/TBCH1–PTF4/TBCH0 pins are the TIMB input
capture/output compare pins. The edge/level select bits,
ELSxB:ELSxA, determine whether the PTF5/TBCH1–PTF4/TBCH0
pins are timer channel I/O pins or general-purpose I/O pins. (See
TIMB Status and Control Register
These read/write bits control port F data direction. Reset clears
DDRF[6:0], configuring all port F pins as inputs.
1 = Corresponding port F pin configured as output
0 = Corresponding port F pin configured as input
$000D
Bit 7
Figure 22-18. Data Direction Register F (DDRF)
R
R
0
0
shows the port F I/O logic.
= Reserved
DDRF6
Input/Output Ports
6
0
Table
DDRF5
5
0
22-6).
DDRF4
4
0
on page 331).
DDRF3
3
0
DDRF2
2
0
Input/Output Ports
DDRF1
1
0
Technical Data
DDRF0
Bit 0
Port F
0
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