XC908AS60ACFU Motorola Semiconductor Products, XC908AS60ACFU Datasheet - Page 516

• Manufacturer Part Number: XC908AS60ACFU
• Description: MC68HC908AZ60A, MC68HC908AS60A Hcmos Microcontroller Unit Technical Data
• Manufacturer: Motorola Semiconductor Products

Byte Data Link Controller (BDLC)
Technical Data
516
.
IE— Interrupt Enable Bit
WCM — Wait Clock Mode Bit
This bit determines whether the BDLC will generate CPU interrupt
requests in run mode. It does not affect CPU interrupt requests when
exiting the BDLC stop or BDLC wait modes. Interrupt requests will be
maintained until all of the interrupt request sources are cleared by
performing the specified actions upon the BDLC’s registers. Interrupts
that were pending at the time that this bit is cleared may be lost.
If the programmer does not wish to use the interrupt capability of the
BDLC, the BDLC state vector register (BSVR) can be polled
periodically by the programmer to determine BDLC states. See
State Vector Register
This bit determines the operation of the BDLC during CPU wait mode.
See
f
1 = Enable interrupt requests from BDLC
0 = Disable interrupt requests from BDLC
1 = Stop BDLC internal clocks during CPU wait mode
0 = Run BDLC internal clocks during CPU wait mode
XCLK
Stop Mode
1.049 MHz
2.097 MHz
4.194 MHz
8.389 MHz
1.000 MHz
2.000 MHz
4.000 MHz
8.000 MHz
Byte Data Link Controller (BDLC)
Frequency
and
Table 27-4. BDLC Rate Selection
Wait Mode
R1
for a description of the BSVR.
0
0
1
1
0
0
1
1
for more details on its use.
R0
0
1
0
1
0
1
0
1
Division
MC68HC908AZ60A — Rev 2.0
1
2
4
8
1
2
4
8
1.049 MHz
1.049 MHz
1.049 MHz
1.049 MHz
1.00 MHz
1.00 MHz
1.00 MHz
1.00 MHz
f
MOTOROLA
BDLC
BDLC