XC908AS60ACFU Motorola Semiconductor Products, XC908AS60ACFU Datasheet - Page 227
XC908AS60ACFU
Manufacturer Part Number
XC908AS60ACFU
Description
MC68HC908AZ60A, MC68HC908AS60A Hcmos Microcontroller Unit Technical Data
Manufacturer
Motorola Semiconductor Products
Datasheet
1.XC908AS60ACFU.pdf
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15.5 COP Control Register
15.6 Interrupts
15.7 Monitor Mode
15.8 Low-Power Modes
15.8.1 Wait Mode
MC68HC908AZ60A — Rev 2.0
MOTOROLA
Address:
The COP control register is located at address $FFFF and overlaps the
reset vector. Writing any value to $FFFF clears the COP counter and
starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
The COP does not generate CPU interrupt requests.
The COP is disabled in monitor mode when V
pin or on the RST pin.
The WAIT and STOP instructions put the MCU in low power-consump-
tion standby modes.
The COP remains active in wait mode. To prevent a COP reset during
wait mode, periodically clear the COP counter in a CPU interrupt routine.
Reset:
Read:
Write:
$FFFF
Computer Operating Properly (COP)
Bit 7
Figure 15-2. COP Control Register (COPCTL)
6
5
Low Byte of Reset Vector
Unaffected by Reset
Clear COP Counter
4
Computer Operating Properly (COP)
3
Hi
is present on the IRQ
2
COP Control Register
1
Technical Data
Bit 0
227
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