XC908AS60ACFU Motorola Semiconductor Products, XC908AS60ACFU Datasheet - Page 495

• Manufacturer Part Number: XC908AS60ACFU
• Description: MC68HC908AZ60A, MC68HC908AS60A Hcmos Microcontroller Unit Technical Data
• Manufacturer: Motorola Semiconductor Products

MC68HC908AZ60A — Rev 2.0
MOTOROLA
NOTE:
IFS — Inter-Frame Separation Symbol
If two messages are received with a 300µs (± 1µs) interframe separation
(IFS) as measured at the RX pin, the start-of-frame (SOF) symbol of the
second message will generate an invalid symbol interrupt. This interrupt
results in the second message being lost and will therefore be
unavailable to the application software. Implementations of this BDLC
design on silicon have not been exposed to interframe separation rates
faster than 320µs in practical application and have therefore previously
not exhibited this behavior. Ensuring that no nodes on the J1850
symbol, if no response is transmitted after an EOD symbol, it
becomes an EOF, and the message is assumed to be completed. The
EOF flag is set upon receiving the EOF symbol.
The IFS symbol is a 20-µs passive period on the J1850 bus which
allows proper synchronization between nodes during continuous
message transmission. The IFS symbol is transmitted by a node after
the completion of the end-of-frame (EOF) period and, therefore, is
seen as a 300-µs passive period.
When the last byte of a message has been transmitted onto the J1850
bus and the EOF symbol time has expired, all nodes then must wait
for the IFS symbol time to expire before transmitting a start-of-frame
(SOF) symbol, marking the beginning of another message.
However, if the BDLC is waiting for the IFS period to expire before
beginning a transmission and a rising edge is detected before the IFS
time has expired, it will synchronize internally to that edge. If a write
to the BDR register (for instance, to initiate transmission) occurred on
or before 104 • t
will transmit and arbitrate for the bus. If a CPU write to the BDR
register occurred after 104 • t
edge, then the BDLC will not transmit, but will wait for the next IFS
period to expire before attempting to transmit the byte.
A rising edge may occur during the IFS period because of varying
clock tolerances and loading of the J1850 bus, causing different
nodes to observe the completion of the IFS period at different times.
To allow for individual clock tolerances, receivers must synchronize to
any SOF occurring during an IFS period.
Byte Data Link Controller (BDLC)
BDLC
from the received rising edge, then the BDLC
BDLC
from the detection of the rising
Byte Data Link Controller (BDLC)
BDLC MUX Interface
Technical Data
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