XC908AS60ACFU Motorola Semiconductor Products, XC908AS60ACFU Datasheet - Page 293

• Manufacturer Part Number: XC908AS60ACFU
• Description: MC68HC908AZ60A, MC68HC908AS60A Hcmos Microcontroller Unit Technical Data
• Manufacturer: Motorola Semiconductor Products

19.6.2 Transmission Format When CPHA = 0
MC68HC908AZ60A — Rev 2.0
MOTOROLA
CAPTURE STROBE
FOR REFERENCE
FROM MASTER
SCK CPOL = 0
SCK CPOL = 1
SCK CYCLE #
SS TO SLAVE
FROM SLAVE
MOSI
MISO
Figure 19-3. Transmission Format (CPHA = 0)
Figure 19-3
logic 0. The figure should not be used as a replacement for data sheet
parametric information. Two waveforms are shown for SCK: one for
CPOL = 0 and another for CPOL = 1. The diagram may be interpreted
as a master or slave timing diagram since the serial clock (SCK), master
in/slave out (MISO), and master out/slave in (MOSI) pins are directly
connected between the master and the slave. The MISO signal is the
output from the slave, and the MOSI signal is the output from the master.
The SS line is the slave select input to the slave. The slave SPI drives
its MISO output only when its slave select input (SS) is at logic 0, so that
only the selected slave drives to the master. The SS pin of the master is
not shown but is assumed to be inactive. The SS pin of the master must
be high or must be reconfigured as general-purpose I/O not affecting the
SPI (see
SPSCK edge is the MSB capture strobe. Therefore, the slave must
begin driving its data before the first SPSCK edge, and a falling edge on
the SS pin is used to start the transmission. The SS pin must be toggled
high and then low again between each byte transmitted.
MSB
MSB
1
Mode Fault Error
BIT 6
BIT 6
Serial Peripheral Interface (SPI)
2
shows an SPI transmission in which CPHA (SPCR) is
BIT 5
BIT 5
3
BIT 4
BIT 4
4
on page 299). When CPHA = 0, the first
BIT 3
BIT 3
5
BIT 2
BIT 2
6
Serial Peripheral Interface (SPI)
BIT 1
BIT 1
7
Transmission Formats
LSB
LSB
8
Technical Data
293