XC908AS60ACFU Motorola Semiconductor Products, XC908AS60ACFU Datasheet - Page 511

• Manufacturer Part Number: XC908AS60ACFU
• Description: MC68HC908AZ60A, MC68HC908AS60A Hcmos Microcontroller Unit Technical Data
• Manufacturer: Motorola Semiconductor Products

27.6.5.5 Summary
MC68HC908AZ60A — Rev 2.0
MOTOROLA
BREAK — Break
Transmission Error
Cyclical Redundancy Check
Invalid Symbol: BDLC Receives
Framing Error
Bus Short to V
Bus Short to GND
BDLC Receives BREAK Symbol.
(CRC) Error
Invalid Bits (Noise)
If a BREAK symbol is received while the BDLC is transmitting or
receiving, an invalid symbol ($1C in BSVR) interrupt will be
generated. Reading the BSVR register (see
Register) will clear this interrupt condition. The BDLC will wait for the
bus to idle, then wait for a start-of-frame (SOF) symbol.
The BDLC cannot transmit a BREAK symbol. It can only receive a
BREAK symbol from the J1850 bus.
Error Condition
Byte Data Link Controller (BDLC)
Table 27-2. BDLC J1850 Bus Error Summary
DD
For invalid bits or framing symbols on non-byte
CRC error interrupt will be generated. The
The BDLC will abort transmission immediately.
Invalid symbol interrupt will be generated. The
The BDLC will not transmit until the bus is idle.
Thermal overload will shut down physical
The BDLC will wait for the next valid SOF.
boundaries, invalid symbol interrupt will be
generated. BDLC stops transmission.
BDLC will wait for SOF.
Invalid symbol interrupt will be generated.
BDLC will wait for start-of-frame (SOF).
interface. Fault condition is reflected in BSVR
as an invalid symbol.
Invalid symbol interrupt will be generated.
Byte Data Link Controller (BDLC)
BDLC Function
BDLC State Vector
BDLC Protocol Handler
Technical Data
511