XC908AS60ACFU Motorola Semiconductor Products, XC908AS60ACFU Datasheet - Page 527

• Manufacturer Part Number: XC908AS60ACFU
• Description: MC68HC908AZ60A, MC68HC908AS60A Hcmos Microcontroller Unit Technical Data
• Manufacturer: Motorola Semiconductor Products

27.8 Low-Power Modes
27.8.1 Wait Mode
MC68HC908AZ60A — Rev 2.0
MOTOROLA
NOTE:
The BDR is double buffered via a transmit shadow register and a receive
shadow register. After the byte in the transmit shift register has been
transmitted, the byte currently stored in the transmit shadow register is
loaded into the transmit shift register. Once the transmit shift register has
shifted the first bit out, the TDRE flag is set, and the shadow register is
ready to accept the next data byte. The receive shadow register works
similarly. Once a complete byte has been received, the receive shift
register stores the newly received byte into the receive shadow register.
The RDRF flag is set to indicate that a new byte of data has been
received. The programmer has one BDLC byte reception time to read
the shadow register and clear the RDRF flag before the shadow register
is overwritten by the newly received byte.
To abort an in-progress transmission, the programmer should stop
loading data into the BDR. This will cause a transmitter underrun error
and the BDLC automatically will disable the transmitter on the next non-
byte boundary. This means that the earliest a transmission can be halted
is after at least one byte plus two extra logic 1s have been transmitted.
The receiver will pick this up as an error and relay it in the state vector
register as an invalid symbol error.
The extra logic 1s are an enhancement to the J1850 protocol which
forces a byte boundary condition fault. This is helpful in preventing noise
from going onto the J1850 bus from a corrupted message.
The following information concerns wait mode and stop mode.
This power-conserving mode is entered automatically from run mode
whenever the CPU executes a WAIT instruction and the WCM bit in
BDLC control register 1 (BCR1) is previously clear. In BDLC wait mode,
the BDLC cannot drive any data.
A subsequent successfully received message, including one that is in
progress at the time that this mode is entered, will cause the BDLC to
Byte Data Link Controller (BDLC)
Byte Data Link Controller (BDLC)
Low-Power Modes
Technical Data
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