XC908AS60ACFU Motorola Semiconductor Products, XC908AS60ACFU Datasheet - Page 525

• Manufacturer Part Number: XC908AS60ACFU
• Description: MC68HC908AZ60A, MC68HC908AS60A Hcmos Microcontroller Unit Technical Data
• Manufacturer: Motorola Semiconductor Products

MC68HC908AZ60A — Rev 2.0
MOTOROLA
Bits I0, I1, I2, and I3 are cleared by a read of the BSVR except when the
BDLC data register needs servicing (RDRF, RXIFR, or TDRE
conditions). RXIFR and RDRF can be cleared only by a read of the
BSVR followed by a read of the BDLC data register (BDR). TDRE can
either be cleared by a read of the BSVR followed by a write to the BDLC
BDR or by setting the TEOD bit in BCR2.
Upon receiving a BDLC interrupt, the user can read the value within the
BSVR, transferring it to the CPU’s index register. The value can then be
used to index into a jump table, with entries four bytes apart, to quickly
enter the appropriate service routine. For example:
BSVR
Service
*
*
JMPTAB
*
$0C
$1C
$00
$04
$08
$10
$14
$18
$20
I3
0
0
0
0
0
0
0
0
1
Byte Data Link Controller (BDLC)
I2
0
0
0
0
1
1
1
1
0
LDX
JMP
JMP
NOP
JMP
NOP
JMP
NOP
JMP
END
Table 27-6. BDLC Interrupt Sources
I1
0
0
1
1
0
0
1
1
0
I0
BSVR
JMPTAB,X
SERVE0
SERVE1
SERVE2
SERVE8
0
1
0
1
0
1
0
1
0
Cyclical Redundancy Check (CRC) Error
BDLC Tx Data Register Empty (TDRE)
BDLC Rx Data Register Full (RDRF)
Symbol Invalid or Out of Range
Received IFR Byte (RXIFR)
No Interrupts Pending
Loss of Arbitration
Interrupt Source
Fetch State Vector Number
Enter service routine,
(must end in RTI)
Service condition #0
Service condition #1
Service condition #2
Service condition #8
Received EOF
Wakeup
Byte Data Link Controller (BDLC)
BDLC CPU Interface
Technical Data
8 (Highest)
0 (Lowest)
Priority
1
2
3
4
5
6
7
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