XC908AS60ACFU Motorola Semiconductor Products, XC908AS60ACFU Datasheet - Page 505

• Manufacturer Part Number: XC908AS60ACFU
• Description: MC68HC908AZ60A, MC68HC908AS60A Hcmos Microcontroller Unit Technical Data
• Manufacturer: Motorola Semiconductor Products

MC68HC908AZ60A — Rev 2.0
MOTOROLA
TRANSMITTER A
TRANSMITTER B
J1850 BUS
PASSIVE
PASSIVE
PASSIVE
ACTIVE
ACTIVE
ACTIVE
Figure 27-11. J1850 VPW Bitwise Arbitrations
The variable pulse width modulation (VPW) symbols and J1850 bus
electrical characteristics are chosen carefully so that a logic 0 (active or
passive type) will always dominate over a logic 1 (active or passive type)
that is simultaneously transmitted. Hence, logic 0s are said to be
dominant and logic 1s are said to be recessive.
Whenever a node detects a dominant bit on BDRxD when it transmitted
a recessive bit, the node loses arbitration and immediately stops
transmitting. This is known as bitwise arbitration.
Since a logic 0 dominates a logic 1, the message with the lowest value
will have the highest priority and will always win arbitration. For instance,
a message with priority 000 will win arbitration over a message with
priority 011.
This method of arbitration will work no matter how many bits of priority
encoding are contained in the message.
During arbitration, or even throughout the transmitting message, when
an opposite bit is detected, transmission is stopped immediately unless
it occurs on the 8th bit of a byte. In this case, the BDLC automatically will
append up to two extra logic 1 bits and then stop transmitting. These two
extra bits will be arbitrated normally and thus will not interfere with
SOF
Byte Data Link Controller (BDLC)
DATA
BIT 1
0
0
0
DATA
BIT 2
1
1
1
DATA
BIT 3
1
1
1
1
DATA
BIT 4
0
0
DATA
BIT 5
0
0
Byte Data Link Controller (BDLC)
TRANSMITTER A DETECTS
AN ACTIVE STATE ON
THE BUS AND STOPS
TRANSMITTING
TRANSMITTER B WINS
ARBITRATION AND
TRANSMITTING
CONTINUES
BDLC MUX Interface
Technical Data
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