XC908AS60ACFU Motorola Semiconductor Products, XC908AS60ACFU Datasheet - Page 519

• Manufacturer Part Number: XC908AS60ACFU
• Description: MC68HC908AZ60A, MC68HC908AS60A Hcmos Microcontroller Unit Technical Data
• Manufacturer: Motorola Semiconductor Products

MC68HC908AZ60A — Rev 2.0
MOTOROLA
TEOD — Transmit End of Data Bit
TSIFR, TMIFR1, and TMIFR0 — Transmit In-Frame Response Control Bits
This bit is set by the programmer to indicate the end of a message is
being sent by the BDLC. It will append an 8-bit CRC after completing
transmission of the current byte. This bit also is used to end an in-
frame response (IFR). If the transmit shadow register is full when
TEOD is set, the CRC byte will be transmitted after the current byte in
the Tx shift register and the byte in the Tx shadow register have been
transmitted. (See
the transmit shadow register.) Once TEOD is set, the transmit data
register empty flag (TDRE) in the BDLC state vector register (BSVR)
is cleared to allow lower priority interrupts to occur. (See
Vector
These three bits control the type of in-frame response being sent. The
programmer should not set more than one of these control bits to a 1
at any given time. However, if more than one of these three control
bits are set to 1, the priority encoding logic will force these register bits
to a known value as shown in
written to TSIFR, TMIFR1, and TMIFR0, then internally they will be
encoded as 010. However, when these bits are read back, they will
read 011.
Write/Read
1 = Transmit end-of-data (EOD) symbol
0 = The TEOD bit will be cleared automatically at the rising edge of
TSIFR
the first CRC bit that is sent or if an error is detected. When
TEOD is used to end an IFR transmission, TEOD is cleared
when the BDLC receives back a valid EOD symbol or an error
condition occurs.
0
1
0
0
Byte Data Link Controller (BDLC)
Register.)
Table 27-5. BDLC Transmit In-Frame Response
Write/Read
TMIFR1
Rx and Tx Shadow Registers
Control Bit Priority Encoding
X
0
1
0
Write/Read
Table
TMIFR0
X
X
0
1
27-5. For example, if 011 is
Byte Data Link Controller (BDLC)
Actual
TSIFR
0
1
0
0
for a description of
TMIFR1
Actual
BDLC CPU Interface
0
0
1
0
BDLC State
Technical Data
TMIFR0
Actual
0
0
0
1
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