XC908AS60ACFU Motorola Semiconductor Products, XC908AS60ACFU Datasheet - Page 554

• Manufacturer Part Number: XC908AS60ACFU
• Description: MC68HC908AZ60A, MC68HC908AS60A Hcmos Microcontroller Unit Technical Data
• Manufacturer: Motorola Semiconductor Products

MC68HC908AS60 and MC68HC908AZ60
29.2.2.2 FLASH Control Registers
29.2.2.3 FLASH Programming Procedure
29.2.2.4 FLASH Programming Time
29.2.2.5 FLASH Block Protection
Technical Data
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row (64 bytes) at a time. Erasing is now carried out on a whole page (128
bytes) at a time. In this new technology an erased bit now reads as a
logic 1 and a programmed bit now reads as a logic 0.
FLASH-1 control register is moved from $FE0B to $FF88. FLASH-2
control register is moved from $FE11 to $FE08. Bits 4 to 7 in the FLASH
control registers are no longer used since clock control is now achieved
automatically and erasing of variable block sizes is no longer a feature.
Bit 2 of the FLASH control registers no longer activates a so-called
‘margin read’ operation but instead is the bit that controls a mass (bulk)
erase operation.
Programming of the FLASH is largely as before within the new
architecture constraints outlined above. However, an extra dummy write
operation to any address in the page is required prior to programming
data into one of the two rows in the page. Margin reading of programmed
data is no longer required. Nor is read / verify / re-pulse of the
programming a requirement.
The most significant change resulting from the new FLASH technology
is that the byte programming time is reduced to a maximum of 40us. This
represents several orders of magnitude improvement from the previous
technology.
The FLASH block protect registers are now 8-bit registers in place of 4-
bit protecting array ranges that can be incremented by as little as 1 page
(128 bytes) at a time as opposed to 8 Kbytes at a time on previous
MCUs. Users making use of the block protect feature must change their
block protect register.
MC68HC908AS60 and MC68HC908AZ60
MC68HC908AZ60A — Rev 2.0
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