XC908AS60ACFU Motorola Semiconductor Products, XC908AS60ACFU Datasheet - Page 305

• Manufacturer Part Number: XC908AS60ACFU
• Description: MC68HC908AZ60A, MC68HC908AS60A Hcmos Microcontroller Unit Technical Data
• Manufacturer: Motorola Semiconductor Products

19.11 Low-Power Modes
19.11.1 Wait Mode
19.11.2 Stop Mode
19.12 SPI During Break Interrupts
MC68HC908AZ60A — Rev 2.0
MOTOROLA
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
The SPI module remains active after the execution of a WAIT instruction.
In wait mode, the SPI module registers are not accessible by the CPU.
Any enabled CPU interrupt request from the SPI module can bring the
MCU out of wait mode.
If SPI module functions are not required during wait mode, reduce power
consumption by disabling the SPI module before executing the WAIT
instruction.
To exit wait mode when an overflow condition occurs, enable the OVRF
bit to generate CPU interrupt requests by setting the error interrupt
enable bit (ERRIE). (See
The SPI module is inactive after the execution of a STOP instruction.
The STOP instruction does not affect register conditions. SPI operation
resumes after the MCU exits stop mode. If stop mode is exited by reset,
any transfer in progress is aborted and the SPI is reset.
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR, $FE03) enables software to
clear status bits during the break state. (See
Register
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
on page 168).
Serial Peripheral Interface (SPI)
Interrupts
on page 301).
Serial Peripheral Interface (SPI)
SIM Break Flag Control
Low-Power Modes
Technical Data
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