XC908AS60ACFU Motorola Semiconductor Products, XC908AS60ACFU Datasheet - Page 514

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XC908AS60ACFU

Manufacturer Part Number
XC908AS60ACFU
Description
MC68HC908AZ60A, MC68HC908AS60A Hcmos Microcontroller Unit Technical Data
Manufacturer
Motorola Semiconductor Products
Datasheet
Byte Data Link Controller (BDLC)
27.7.2 BDLC Control Register 1
Technical Data
514
Address:
B03–B00 — BARD Offset Bits
This register is used to configure and control the BDLC.
Reset:
Read:
Write:
BARD Offset Bits B0[3:0]
Table 27-3
BARD offset values.
$003C
Table 27-3. BDLC Transceiver Delay
IMSG
Bit 7
R
1
Byte Data Link Controller (BDLC)
Figure 27-16. BDLC Control Register 1 (BCR1)
0000
0001
0010
0100
0101
1000
1001
1010
0011
0110
0111
1011
1100
1101
1110
1111
shows the expected transceiver delay with respect to
= Reserved
CLKS
6
1
R1
5
1
Transceiver’s Delays ( µ s)
Corresponding Expected
R0
4
0
10
12
13
14
15
16
17
18
19
20
21
22
23
24
11
9
R
3
0
0
MC68HC908AZ60A — Rev 2.0
R
2
0
0
IE
1
0
MOTOROLA
WCM
Bit 0
0

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