XC908AS60ACFU Motorola Semiconductor Products, XC908AS60ACFU Datasheet - Page 358

• Manufacturer Part Number: XC908AS60ACFU
• Description: MC68HC908AZ60A, MC68HC908AS60A Hcmos Microcontroller Unit Technical Data
• Manufacturer: Motorola Semiconductor Products

Input/Output Ports
22.4.2 Data Direction Register B
Technical Data
358
NOTE:
Address:
ATD[7:0] — ADC Channels
Data direction register B determines whether each port B pin is an input
or an output. Writing a logic 1 to a DDRB bit enables the output buffer for
the corresponding port B pin; a logic 0 disables the output buffer.
DDRB[7:0] — Data Direction Register B Bits
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
Figure 22-7
Reset:
Read:
Write:
PTB7/ATD7–PTB0/ATD0 are eight of the analog-to-digital converter
channels. The ADC channel select bits, CH[4:0], determine whether
the PTB7/ATD7–PTB0/ATD0 pins are ADC channels or general-
purpose I/O pins. If an ADC channel is selected and a read of this
corresponding bit in the port B data register occurs, the data will be 0
if the data direction for this bit is programmed as an input. Otherwise,
the data will reflect the value in the data latch. (See
Converter (ADC)
does not affect the data direction of port B pins that are being used by
the ADC. However, the DDRB bits always determine whether reading
port B returns to the states of the latches or logic 0.
These read/write bits control port B data direction. Reset clears
DDRB[7:0], configuring all port B pins as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
DDRB7
$0005
Bit 7
0
Figure 22-6. Data Direction Register B (DDRB)
shows the port B I/O logic.
DDRB6
Input/Output Ports
6
0
on page 471). Data direction register B (DDRB)
DDRB5
5
0
DDRB4
4
0
DDRB3
3
0
MC68HC908AZ60A — Rev 2.0
DDRB2
2
0
Analog-to-Digital
DDRB1
1
0
MOTOROLA
DDRB0
Bit 0
0