XC908AS60ACFU Motorola Semiconductor Products, XC908AS60ACFU Datasheet - Page 367
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XC908AS60ACFU
Manufacturer Part Number
XC908AS60ACFU
Description
MC68HC908AZ60A, MC68HC908AS60A Hcmos Microcontroller Unit Technical Data
Manufacturer
Motorola Semiconductor Products
Datasheet
1.XC908AS60ACFU.pdf
(576 pages)
- Current page: 367 of 576
- Download datasheet (4Mb)
MC68HC908AZ60A — Rev 2.0
MOTOROLA
NOTE:
NOTE:
MISO — Master In/Slave Out Bit
SS — Slave Select Bit
Data direction register E (DDRE) does not affect the data direction of
port E pins that are being used by the SPI module. However, the DDRE
bits always determine whether reading port E returns the states of the
latches or the states of the pins. (See
TACH[1:0] — Timer Channel I/O Bits
Data direction register E (DDRE) does not affect the data direction of
port E pins that are being used by the TIM. However, the DDRE bits
always determine whether reading port E returns the states of the
latches or the states of the pins. (See
RxD — SCI Receive Data Input Bit
The PTE5/MISO pin is the master in/slave out terminal of the SPI
module. When the SPI enable bit, SPE, is clear, the SPI module is
disabled, and the PTE5/MISO pin is available for general-purpose
I/O. (See
The PTE4/SS pin is the slave select input of the SPI module. When
the SPE bit is clear, or when the SPI master bit, SPMSTR, is set and
MODFEN bit is low, the PTE4/SS pin is available for general-purpose
I/O. (See
as a slave, the DDRF0 bit in data direction register E (DDRE) has no
effect on the PTE4/SS pin.
The PTE3/TACH1–PTE2/TACH0 pins are the TIM input
capture/output compare pins. The edge/level select bits,
ELSxB:ELSxA, determine whether the PTE3/TACH1–PTE2/TACH0
pins are timer channel I/O pins or general-purpose I/O pins. (See
TIMA Channel Status and Control Registers
The PTE1/RxD pin is the receive data input for the SCI module. When
the enable SCI bit, ENSCI, is clear, the SCI module is disabled, and
the PTE1/RxD pin is available for general-purpose I/O. (See
Control Register 1
SPI Control Register
SS (Slave Select)
Input/Output Ports
on page 265).
on page 308). When the SPI is enabled
on page 310).
Table
Table
22-5).
22-5).
on page 462).
Input/Output Ports
Technical Data
SCI
Port E
367
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