XC908AS60ACFU Motorola Semiconductor Products, XC908AS60ACFU Datasheet - Page 456

• Manufacturer Part Number: XC908AS60ACFU
• Description: MC68HC908AZ60A, MC68HC908AS60A Hcmos Microcontroller Unit Technical Data
• Manufacturer: Motorola Semiconductor Products

Timer Interface Module A (TIMA)
25.8 I/O Signals
25.8.1 TIMA Clock Pin (PTD6/ATD14/
TACLK)
25.8.2 TIMA Channel I/O Pins (PTF3–PTF0/TACH2 and PTE3/TACH1–PTE2/TACH0)
Technical Data
456
status bits have a 2-step read/write clearing procedure. If software does
the first step on such a bit before the break, the bit cannot change during
the break state as long as BCFE is at logic 0. After the break, doing the
second step clears the status bit.
Port D shares one of its pins with the TIMA. Port E shares two of its pins
with the TIMA and port F shares four of its pins with the TIMA.
PTD6/ATD14/TACLK is an external clock input to the TIMA prescaler.
The six TIMA channel I/O pins are PTE2/TACH0, PTE3/TACH1,
PTF0/TACH2, PTF1/TACH3, PTF2, and PTF3.
PTD6/ATD14/TACLK is an external clock input that can be the clock
source for the TIMA counter instead of the prescaled internal bus clock.
Select the PTD6/ATD14/TACLK input by writing logic 1s to the three
prescaler select bits, PS[2:0] (see
The minimum TCLK pulse width, TCLK
The maximum TCLK frequency is the least: 4 MHz or bus frequency ÷ 2.
PTD6/ATD14/TACLK is available as a general-purpose I/O pin or ADC
channel when not used as the TIMA clock input. When the
PTD6/ATD14/TACLK pin is the TIMA clock input, it is an input regardless
of the state of the DDRD6 bit in data direction register D.
Each channel I/O pin is programmable independently as an input
capture pin or an output compare pin. PTE2/TACH0, PTF0/TACH2 and
PTF2 can be configured as buffered output compare or buffered PWM
pins.
Timer Interface Module A (TIMA)
------------------------------------ -
bus frequency
1
TIMA Status and Control
LMIN
+
t
or TCLK
SU
MC68HC908AZ60A — Rev 2.0
HMIN
, is:
Register).
MOTOROLA