XC908AS60ACFU Motorola Semiconductor Products, XC908AS60ACFU Datasheet - Page 496

• Manufacturer Part Number: XC908AS60ACFU
• Description: MC68HC908AZ60A, MC68HC908AS60A Hcmos Microcontroller Unit Technical Data
• Manufacturer: Motorola Semiconductor Products

Byte Data Link Controller (BDLC)
27.5.3 J1850 VPW Symbols
Technical Data
496
NOTE:
network transmit messages at 300µs (± 1µs) IFS will avoid this missed
message frame. In addition, developing application software to robustly
handle lost messages will minimize application impact.
BREAK — Break
The J1850 protocol BREAK symbol is not related to the HC08 break
module. See
IDLE — Idle Bus
Huntsinger’s variable pulse width modulation (VPW) is an encoding
technique in which each bit is defined by the time between successive
transitions and by the level of the bus between transitions (for instance,
active or passive). Active and passive bits are used alternately. This
encoding technique is used to reduce the number of bus transitions for
a given bit rate.
Each logic 1 or logic 0 contains a single transition and can be at either
the active or passive level and one of two lengths, either 64 µs or 128 µs
The BDLC cannot transmit a BREAK symbol.
If the BDLC is transmitting at the time a BREAK is detected, it treats
the BREAK as if a transmission error had occurred and halts
transmission.
If the BDLC detects a BREAK symbol while receiving a message, it
treats the BREAK as a reception error and sets the invalid symbol flag
in the BSVR, also ignoring the frame it was receiving. If while
receiving a message in 4X mode, the BDLC detects a BREAK
symbol, it treats the BREAK as a reception error, sets the invalid
symbol flag, and exits 4X mode (for example, the RX4XE bit in BCR2
is cleared automatically). If bus control is required after the BREAK
symbol is received and the IFS time has elapsed, the programmer
must resend the transmission byte using highest priority.
An idle condition exists on the bus during any passive period after
expiration of the IFS period (for instance, ≥ 300 µs). Any node sensing
an idle bus condition can begin transmission immediately.
Byte Data Link Controller (BDLC)
Break Module (BRK)
on page 203.
MC68HC908AZ60A — Rev 2.0
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