XC908AS60ACFU Motorola Semiconductor Products, XC908AS60ACFU Datasheet - Page 185

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XC908AS60ACFU

Manufacturer Part Number
XC908AS60ACFU
Description
MC68HC908AZ60A, MC68HC908AS60A Hcmos Microcontroller Unit Technical Data
Manufacturer
Motorola Semiconductor Products
Datasheet
10.6.2 PLL Bandwidth Control Register
MC68HC908AZ60A — Rev 2.0
MOTOROLA
Address:
(PLLON = 0), selecting CGMVCLK requires two writes to the PLL control
register. See
PCTL3–PCTL0 — Unimplemented
The PLL bandwidth control register:
Reset:
Read:
Write:
These bits provide no function and always read as logic 1s.
Selects automatic or manual (software-controlled) bandwidth
control mode
Indicates when the PLL is locked
In automatic bandwidth control mode, indicates when the PLL is in
acquisition or tracking mode
In manual operation, forces the PLL into acquisition or tracking
mode
Figure 10-5. PLL Bandwidth Control Register (PBWC)
$001D
AUTO
Bit 7
0
Clock Generator Module (CGM)
Base Clock Selector Circuit
= Unimplemented
LOCK
6
0
ACQ
5
0
XLD
4
0
3
0
0
on page 179.
Clock Generator Module (CGM)
2
0
0
CGM Registers
1
0
0
Technical Data
Bit 0
0
0
185

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