XC908AS60ACFU Motorola Semiconductor Products, XC908AS60ACFU Datasheet - Page 517

• Manufacturer Part Number: XC908AS60ACFU
• Description: MC68HC908AZ60A, MC68HC908AS60A Hcmos Microcontroller Unit Technical Data
• Manufacturer: Motorola Semiconductor Products

27.7.3 BDLC Control Register 2
MC68HC908AZ60A — Rev 2.0
MOTOROLA
Address:
This register controls transmitter operations of the BDLC. It is
recommended that BSET and BCLR instructions be used to manipulate
data in this register to ensure that the register’s content does not change
inadvertently.
ALOOP — Analog Loopback Mode Bit
Reset:
Read:
Write:
This bit determines whether the J1850 bus will be driven by the
analog physical interface’s final drive stage. The programmer can use
this bit to reset the BDLC state machine to a known state after the off-
chip analog transceiver is placed in loopback mode. When the user
clears ALOOP, to indicate that the off-chip analog transceiver is no
longer in loopback mode, the BDLC waits for an EOF symbol before
attempting to transmit.
1 = Input to the analog physical interface’s final drive stage is
0 = The J1850 bus will be driven by the BDLC. After the bit is
ALOOP
$003D
Bit 7
looped back to the BDLC receiver. The J1850 bus is not driven.
cleared, the BDLC requires the bus to be idle for a minimum of
end-of-frame symbol time (t
a minimum of inter-frame symbol time (t
transmission. (See
Timings.)
1
Figure 27-17. BDLC Control Register 2 (BCR2)
Byte Data Link Controller (BDLC)
DLOOP
6
1
RX4XE
5
0
BDLC Transmitter VPW Symbol
NBFS
4
0
TRV4
TEOD
) before message reception or
3
0
Byte Data Link Controller (BDLC)
TSIFR
TRV6
2
0
) before message
BDLC CPU Interface
TMIFR1
1
0
Technical Data
TMIFR0
Bit 0
0
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