XC908AS60ACFU Motorola Semiconductor Products, XC908AS60ACFU Datasheet - Page 198

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XC908AS60ACFU

Manufacturer Part Number
XC908AS60ACFU
Description
MC68HC908AZ60A, MC68HC908AS60A Hcmos Microcontroller Unit Technical Data
Manufacturer
Motorola Semiconductor Products
Datasheet
Configuration Register (CONFIG-1)
Technical Data
198
NOTE:
Address:
for at least nine consecutive CPU cycles. Once an LVI reset occurs, the
MCU remains in reset until V
LVISTOP — LVI Stop Mode Enable Bit
To have the LVI enabled in stop mode, the LVIPWR must be at a logic 1
and the LVISTOP bit must be at a logic 1. Take note that by enabling the
LVI in stop mode, the stop I
LVIRST — LVI Reset Enable Bit
Reset:
Read:
Write:
LVISTOP enables the LVI module in stop mode. (See
Inhibit (LVI)
LVIRST enables the reset signal from the LVI module. (See
Voltage Inhibit (LVI)
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
1 = LVI module resets enabled
0 = LVI module resets disabled
LVISTOP
$001F
Bit 7
Configuration Register (CONFIG-1)
Figure 11-1. Configuration Register (CONFIG-1)
R
0
= Reserved
on page 229).
R
6
1
LVIRST
on page 229).
5
1
DD
DD
current will be higher.
LVIPWR
rises to a voltage, LVI
4
1
SSREC
3
0
MC68HC908AZ60A — Rev 2.0
COPL
2
0
TRIPR
Low Voltage
STOP
1
0
.
MOTOROLA
Low
COPD
Bit 0
0

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