dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 107
dsp56000
Manufacturer Part Number
dsp56000
Description
24-bit Digital Signal Processor Family Manual
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.DSP56000.pdf
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6.3.4.4.2
The operand, a word reference, is in Y memory space. Data can be transferred from mem-
ory to a register or from a register to memory.
6.3.4.4.3
Long (L) memory space references both X and Y memory spaces with one operand
address. The data operand is a long-word reference developed by concatenating the X
and Y memory spaces (X:Y). The high-order word of the operand is in the X memory; the
low-order word of the operand is in the Y memory. Data can be read from memory to con-
catenated registers X1:X0, A1:A0, etc. or from concatenated registers to memory.
6.3.4.4.4
XY memory space references both X and Y memory spaces with two operand addresses.
Two independent addresses are used to access two word operands – one word operand
is in X memory space, and one word operand is in Y memory space. Two effective
addresses in the instruction are used to derive two independent operand addresses – one
operand address may reference either X or Y memory space and the other operand
address must reference the other memory space. One of these two effective addresses
specified in the instruction must reference one of the address registers, R0–R3, and the
other effective address must reference one of the address registers, R4–R7. Addressing
modes are restricted to no-update and post-update by +1, –1, and +N addressing modes.
Each effective address provides independent read/write control for its memory space.
Data may be read from memory to a register or from a register to memory.
6.3.5 Addressing Modes
The DSP instruction set contains a full set of operand addressing modes. To minimize
execution time and loop overhead, all address calculations are performed concurrently in
the address ALU.
Addressing modes specify whether the operand(s) is in a register or in memory, and pro-
vide the specific address of the operand(s). An effective address in an instruction will
specify an addressing mode, and, for some addressing modes, the effective address will
further specify an address register. In addition, address register indirect modes require
additional address modifier information that is not encoded in the instruction. The address
modifier information is specified in the selected address modifier register(s). All indirect
memory references require one address modifier, and the XY memory reference requires
two address modifiers. The definition of certain instructions implies the use of specific reg-
isters and addressing modes.
MOTOROLA
Y Memory References
L Memory References
YX Memory References
Freescale Semiconductor, Inc.
INSTRUCTION SET INTRODUCTION
For More Information On This Product,
INSTRUCTION FORMATS
Go to: www.freescale.com
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