dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 572

• Manufacturer Part Number: dsp56000
• Description: 24-bit Digital Signal Processor Family Manual
• Manufacturer: Freescale Semiconductor, Inc

A.9.1 Restrictions Near the End of DO Loops
Proper DO loop operation is not guaranteed if an instruction starting at address LA–2,
LA–1, or LA specifies one of the program controller registers SR, SP, SSL, LA, LC, or
(implicitly) PC as a destination register. Similarly, the SSH register may not be specified
as a source or destination register in an instruction starting at address LA–2, LA–1, or
LA. Additionally, the SSH register cannot be specified as a source register in the DO
instruction itself, and LA cannot be used as a target for jumps to subroutine (i.e., JSR,
JScc, JSSET, or JSCLR to LA). The following instructions cannot begin at the indicated
position(s) near the end of a DO loop:
At LA–2, LA–1, and LA
At LA
*This restriction applies to the situation in which the DSP56K simulator’s single-line
assembler is used to change the last instruction in a DO loop from a one-word instruc-
tion to a two-word instruction. All changes made using the simulator should be reassem-
bled at the source code level using the DSP56K macro assembler to verify that no
restricted instruction sequences have been generated.
A - 306
INSTRUCTION SEQUENCE RESTRICTIONS
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INSTRUCTION SET DETAILS
DO
BCHG LA, LC, SR, SP, SSH, or SSL
BCLR LA, LC, SR, SP, SSH, or SSL
BSET LA, LC, SR, SP, SSH, or SSL
BTST SSH
JCLR/JSET/JSCLR/JSSET SSH
MOVEC from SSH
MOVEM from SSH
MOVEP from SSH
MOVEC to LA, LC, SR, SP, SSH, or SSL
MOVEM to LA, LC, SR, SP, SSH, or SSL
MOVEP to LA, LC, SR, SP, SSH, or SSL
ANDI MR
ORI MR
any two-word instruction
Jcc
JMP
JScc
JSR
REP
RESET
RTI
RTS
STOP
WAIT
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