dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 135

• Manufacturer Part Number: dsp56000
• Description: 24-bit Digital Signal Processor Family Manual
• Manufacturer: Freescale Semiconductor, Inc

the main uses of interrupts is to transfer data between DSP memory or registers and a
peripheral device. When such an interrupt occurs, a limited context switch with minimal
overhead is ideal. A fast interrupt accomplishes a limited context switch. The processor
relies on a long interrupt when it must accomplish a more complex task to service the
interrupt. Fast interrupts and long interrupts are described in more detail in Section 7.3.1.
There are many sources for interrupts on the DSP56K family of chips, and some of these
sources can generate more than one interrupt. The DSP56K family of processors fea-
tures a prioritized interrupt vector scheme with 32 vectors to provide fast interrupt ser-
vice. The interrupt priority structure is discussed in Section 7.3.2. The following list
outlines how the DSP56K processes interrupts:
If neither instruction is a change of program-flow instruction (i.e., a JSR), the state of the
machine is not saved on the stack, and a fast interrupt is executed. A long interrupt
occurs if one of the interrupt instructions fetched is a JSR instruction. The PC is immedi-
ately released, the SR and the PC are saved in the stack, and the jump instruction con-
trols where the next instruction shall be fetched. While either an unconditional jump or a
conditional jump can be used to form a long interrupt, they do not store the PC on the
stack. Therefore, there is no return path.
Activities 2 and 3 listed above require two additional control cycles, which effectively
make the interrupt pipeline five levels deep.
7.3.1 Interrupt Types
The DSP56K relies on two types of interrupt routines: fast and long. The fast interrupt
MOTOROLA
1. A hardware interrupt is synchronized with the DSP clock, and the interrupt
2. All pending interrupts (external and internal) are arbitrated to select which
3. The interrupt controller then freezes the program counter (PC) and fetches two
4. The interrupt controller jams the two instructions into the instruction stream
pending flag for that particular hardware interrupt is set. An interrupt source
can have only one interrupt pending at any given time.
interrupt will be processed. The arbiter automatically ignores any interrupts
with an IPL lower than the interrupt mask level in the SR and selects the
remaining interrupt with the highest IPL.
instructions at the two interrupt vector addresses associated with the selected
interrupt.
and releases the PC, which is used for the next instruction fetch. The next
interrupt arbitration then begins.
EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING)
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