dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 153

• Manufacturer Part Number: dsp56000
• Description: 24-bit Digital Signal Processor Family Manual
• Manufacturer: Freescale Semiconductor, Inc

The execution of a long interrupt routine always conforms to the following rules:
Figure 7-10 illustrates the effect of a long interrupt routine on the instruction pipeline. A
short JSR (a JSR with 12-bit absolute address) is used to form the long interrupt routine.
For this example, word 6 of the long interrupt routine is an RTI. The point at which inter-
rupts are re-enabled and subsequent interrupts are allowed is shown to illustrate the
non-interruptible nature of the early instructions in the long interrupt service routine.
Either one of the two instructions of the fast interrupt can be the JSR instruction that
forms the long interrupt. Figure 7-11 and Figure 7-12 show the two possible cases. If the
first fast interrupt vector instruction is the JSR, the second instruction is never used.
A REP instruction and the instruction that follows it are treated as a single two-word
instruction, regardless of how many times it repeats the second instruction of the pair.
Instruction fetches are suspended and will be reactivated only after the LC is decre-
MOTOROLA
6. The fast interrupt returns without an RTI.
7. Normal instruction fetching resumes using the PC following the completion of
8. A fast interrupt is not interruptible.
9. A JSR instruction within the fast interrupt routine forms a long interrupt routine.
10. The primary application is to move data between memory and I/O devices.
1. A JSR to the starting address of the interrupt service routine is located at one
2. During execution of the JSR instruction, the PC and SR are stacked. The inter-
3. The first instruction word of the next interrupt service (of higher IPL) will reach
4. The interrupt service routine can be interrupted — i.e., nested interrupts are
5. The long interrupt routine, which can be any length, should be terminated by
the fast interrupt routine.
of the two interrupt vector addresses.
rupt mask bits of the SR are updated to mask interrupts of the same or lower
priority. The loop flag, trace bit, double precision multiply mode bit, and scaling
mode bits are reset.
the decoder only after the decoding of at least four instructions following the
decoding of the first instruction of the previous interrupt.
supported.
an RTI, which restores the PC and SR from the stack.
EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING)
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PROCESSING STATES
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