dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 524

• Manufacturer Part Number: dsp56000
• Description: 24-bit Digital Signal Processor Family Manual
• Manufacturer: Freescale Semiconductor, Inc

Operation:
Description: Round the 56-bit value in the specified destination operand D and store the
result in the MSP portion of the destination accumulator (A1 or B1). This instruction uses
a convergent rounding technique. The contribution of the LS bits of the result (A0 and
B0) is rounded into the upper portion of the result (A1 or B1) by adding a rounding con-
stant to the LS bits of the result. The MSP portion of the destination accumulator con-
tains the rounded result which may be read out to the data buses.
The value of the rounding constant added is determined by the scaling mode bits S0 and
S1 in the system status register (SR). A “1” is added in the rounding position as shown
below:
Normal or “standard’’ rounding consists of adding a rounding constant to a given
number of LS bits of a value to produce a rounded result. The rounding constant
depends on the scaling mode being used as previously shown. Unfortunately, when
using a twos-complement data representation, this process introduces a positive bias in
the statistical distribution of the roundoff error.
A - 258
RND
S1
0
0
1
D+r
S0
0
1
0
D (parallel move)
Scaling Mode
Scale Down
No Scaling
Scale Up
Freescale Semiconductor, Inc.
For More Information On This Product,
INSTRUCTION DESCRIPTIONS
INSTRUCTION SET DETAILS
Rounding
Position
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Round Accumulator
23
24
22
55 - 25
0. . . .0
0. . . .0
0. . . .0
Assembler Syntax:
RND D (parallel move)
Rounding Constant
24
0
1
0
23
1
0
0
22
0
0
1
MOTOROLA
RND
0. . . .0
0. . . .0
0. . . .0
21 - 0