dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 544

• Manufacturer Part Number: dsp56000
• Description: 24-bit Digital Signal Processor Family Manual
• Manufacturer: Freescale Semiconductor, Inc

Operation:
Description: Subtract the source operand S from two times the destination operand D
and store the result in the destination accumulator. The destination operand D is arith-
metically shifted one bit to the left, and a zero is shifted into the LS bit of D prior to the
subtraction operation. The carry bit is set correctly if the source operand does not over-
flow as a result of the left shift operation. The overflow bit may be set as a result of either
the shifting or subtraction operation (or both). This instruction is useful for efficient divide
and decimation in time (DIT) FFT algorithms.
Example:
Explanation of Example: Prior to execution, the 56-bit A accumulator contains the
value $00:004000:000000, and the 56-bit B accumulator contains the value
$00:005000:000000. The SUBL A,B instruction subtracts the value in the A accumulator
from two times the value in the B accumulator and stores the 56-bit result in the B accu-
mulator.
A - 278
SUBL
2 D–S
SUBL A,B
A
B
:
:
D (parallel move)
$00:004000:000000
$00:005000:000000
Before Execution
Y:(R5+N5),R7
Freescale Semiconductor, Inc.
For More Information On This Product,
Shift Left and Subtract Accumulators
INSTRUCTION DESCRIPTIONS
INSTRUCTION SET DETAILS
Go to: www.freescale.com
;2 B–A
Assembler Syntax:
A
B
B, load R7, no R5 update
SUBL
$00:004000:000000
$00:006000:000000
After Execution
S,D (parallel move)
SUBL
MOTOROLA