dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 345
dsp56000
Manufacturer Part Number
dsp56000
Description
24-bit Digital Signal Processor Family Manual
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.DSP56000.pdf
(637 pages)
- Current page: 345 of 637
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DEBUGcc
Example:
Explanation of Example: The results of the comparison between Y0 and B will be
recorded in the status register bits. The conditional debug instruction looks at the condi-
tions (for greater than or equal in this case) and if they are met (N
DEBUG instruction will be executed. The chip enters the debug mode after the instruc-
tion following the DEBUG instruction has entered the instruction latch. The chip pulses
low the DSO line to inform the external command controller that it has entered the debug
mode and that the chip is waiting for commands.
Instruction Format:
Opcode:
Instruction Fields:
Mnemonic
CC (HS)
GE
NE
PL
NN
EC
LC
GT
Timing: 4 oscillator clock cycles
Memory: 1 program word
MOTOROLA
CMP
DEBUGge
DEBUGcc
23
0
Y0,
0
:
:
0
0
0
0
0
0
0
0
0
c c c c
0
B
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0
Freescale Semiconductor, Inc.
0
For More Information On This Product,
Enter Debug Mode Conditionally
0
INSTRUCTION DESCRIPTIONS
INSTRUCTION SET DETAILS
16 15
0
Go to: www.freescale.com
0
0
Mnemonic
CS (LO)
LT
EQ
MI
NR
ES
LS
LE
; Compare register Y0 with the B accumulator.
; Enter the debug mode if
; the previous test result is “greater than”.
0
0
0
0
1
c c c c
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
8
1
7
0
0
DEBUGcc
0
0
c
V=0) then the
c
c
0
c
A - 79
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