dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 18

• Manufacturer Part Number: dsp56000
• Description: 24-bit Digital Signal Processor Family Manual
• Manufacturer: Freescale Semiconductor, Inc

The DSP56K family is not designed for a particular application but is designed to execute
commonly used DSP benchmarks in a minimum time for a single-multiplier architecture.
For example, a cascaded, 2nd-order, four-coefficient infinite impulse response (IIR) bi-
quad section has four multiplies for each section. For that algorithm, the theoretical
minimum number of operations for a single-multiplier architecture is four per section. Ta-
ble 1-1 shows a list of benchmarks with the number of instruction cycles a DSP56K chip
uses compared to the number of multiplies the algorithm requires.
These benchmarks and others are used independently or in combination to implement
functions whose characteristics are controlled by the coefficients of the benchmarks being
executed. Useful functions using these and other benchmarks include the following:
1- 6
Real Multiply
N Real Multiplies
Real Update
N Real Updates
N Term Real Convolution (FIR)
N Term Real * Complex Convolution
Complex Multiply
N Complex Multiplies
Complex Update
N Complex Updates
N Term Complex Convolution (FIR)
N
2
N Cascaded 2
N Radix Two FFT Butterflies
nd
th
- Order Power Series
- Order Real Biquad Filter
Table 1-1 Benchmark Summary in Instruction Cycles
Benchmark
nd
- Order Biquads
ORIGIN OF DIGITAL SIGNAL PROCESSING
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Number of Cycles
2N
2N
2N
4N
4N
4N
2N
4N
6N
N
3
4
6
7
7
Number of
Algorithm
Multiplies
4N
4N
2N
4N
4N
N
N
N
N
N
1
1
4
4
4
MOTOROLA