dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 351

• Manufacturer Part Number: dsp56000
• Description: 24-bit Digital Signal Processor Family Manual
• Manufacturer: Freescale Semiconductor, Inc

Note that the divide routine used in the previous example assumes that the sign-
extended 56-bit signed fractional dividend is stored in the A accumulator and that the 24-
bit signed fractional divisor is stored in the X0 register. This routine produces a full 24-bit
signed quotient and a 48-bit signed remainder.
This routine may be greatly simplified for the case in which only positive, fractional oper-
ands are used to produce a 24-bit positive quotient and a 48-bit positive remainder, as
shown in the following example:
Note that this routine assumes that the 56-bit positive, fractional, sign-extended dividend
is stored in the A accumulator and that the 24-bit positive, fractional divisor is stored in
the X0 register. After execution, the 24-bit positive fractional quotient is stored in the A0
register; the LS 24 bits of the 48-bit positive fractional remainder are stored in the A1 reg-
ister.
There are many variations possible when choosing a suitable division routine for a given
application. The selection of a suitable division routine normally involves specification of
the following items:
MOTOROLA
DIV
1-Quadrant division, 24-bit unsigned quotient, 48-bit unsigned remainder
AND #$FE,CCR
REP #$18
DIV X0,A
ADD X0,A
1. the number of bits of precision in the dividend;
2. the number of bits of precision N in the quotient;
3. whether the value of N is fixed or is variable;
4. whether the operands are unsigned or signed;
5. whether or not the remainder is to be calculated.
Freescale Semiconductor, Inc.
For More Information On This Product,
;clear carry bit C (quotient sign bit)
;form a 24-bit quotient and remainder
;form quotient in A0, remainder in A1
;restore remainder in A1
INSTRUCTION DESCRIPTIONS
INSTRUCTION SET DETAILS
Go to: www.freescale.com
Divide Interation
DIV
A - 85