dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 271
dsp56000
Manufacturer Part Number
dsp56000
Description
24-bit Digital Signal Processor Family Manual
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.DSP56000.pdf
(637 pages)
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MOTOROLA
Xn
Yn
An
Bn
X
Y
A
B
AB
BA
A10
B10
* NOTE: In data move operations, shifting and limiting are performed when this register is specified
Rn
Nn
Mn
as a source operand. When specified as a destination operand, sign extension and possibly
zeroing are performed.
Input Register X1 or X0 (24 Bits)
Input Register Y1 or Y0 (24 Bits)
Accumulator Registers A2, A1, A0 (A2 — 8 Bits, A1 and A0 — 24 Bits)
Accumulator Registers B2, B1, B0 (B2 — 8 Bits, B1 and B0 — 24 Bits)
Input Register X = X1: X0 (48 Bits)
Input Register Y = Y1: Y0 (48 Bits)
Accumulator A = A2: A1: A0 (56 Bits)*
Accumulator B = B2: B1: B0 (56 BIts)*
Accumulators A and B = A1: B1 (48 Bits)*
Accumulators B and A = B1: A1 (48 Bits)*
Accumulator A = A1: A0 (48 Bits)
Accumulator B= B1:B0 (48 bits)
Address Registers R0 - R7 (16 Bits)
Address Offset Registers N0 - N7 (16 Bits)
Address Modifier Registers M0 - M7 (16 Bits)
Table A-1 Instruction Description Notation
Freescale Semiconductor, Inc.
For More Information On This Product,
Address ALU Registers Operands
INSTRUCTION SET DETAILS
Data ALU Registers Operands
Go to: www.freescale.com
NOTATION
A - 5
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