dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 150

• Manufacturer Part Number: dsp56000
• Description: 24-bit Digital Signal Processor Family Manual
• Manufacturer: Freescale Semiconductor, Inc

7.3.7 Interrupt Instruction Execution
Interrupt instruction execution is considered “fast” if neither of the instructions of the
interrupt service routine causes a change of flow. A JSR within a fast interrupt routine
forms a long interrupt, which is terminated with an RTI instruction to restore the PC and
SR from the stack and return to normal program execution. Reset is a special exception,
which will normally contain only a JMP instruction at the exception start address. At the
programmer’s option, almost any instruction can be used in the fast interrupt routine. The
restricted instructions include SWI, STOP, and WAIT. Figure 7-8 and Figure 7-10 show
the fast and the long interrupt service routines. The fast interrupt executes only two
instructions and then automatically resumes execution of the main program; whereas,
the long interrupt must be told to return to the main program by executing an RTI instruc-
tion.
Figure 7-8 illustrates the effect of a fast interrupt routine in the stream of instruction
fetches.
Figure 7-9 shows the sequence of instruction decodes between two fast interrupts. Four
decodes occur between the two interrupt decodes (two after the first interrupt and two
preceding the second interrupt). The requirement for these four decodes establishes the
maximum rate at which the DSP56K will respond to interrupts — namely, one interrupt
every six instructions (six instruction cycles if all six instructions are one instruction cycle
each). Since some instructions take more than one instruction cycle, the minimum num-
ber of instructions between two interrupts may be more than six instruction cycles.
The execution of a fast interrupt routine always conforms to the following rules:
7 - 26
1. A JSR to the starting address of the interrupt service routine is not located at
2. The processor status is not saved.
3. The fast interrupt routine may (but should not) modify the status of the normal
4. The fast interrupt routine may contain any single two-word instruction or any
5. The PC, which contains the address of the next instruction to be executed in
one of the two interrupt vector addresses.
instruction stream.
two one-word instructions except SWI, STOP, and WAIT.
normal processing remains unchanged during a fast interrupt routine.
EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING)
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