dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 618

• Manufacturer Part Number: dsp56000
• Description: 24-bit Digital Signal Processor Family Manual
• Manufacturer: Freescale Semiconductor, Inc

B - 14
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;Motorola Austin DSP Operation
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;DSP56000/1
;8-pole 4-multiply cascaded canonic IIR filter
;File name: 4-56.asm
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Figure B-5 Real Input FFT Based on Glenn Bergland Algorithm (Sheet 3 of 8)
page 132,66,0,6
opt
Maximum sample rate: 410.0 kHz at 20.5 MHz/540.0 kHz at 27.0 MHz
Memory Size: Prog: 6+10 words; Data: 4(2+4) words
Number of clock cycles: 50 (25 instruction cycles)
Clock Frequency: 20.5 MHz/27.0 MHz
Instruction cycle time: 97.5 ns/74.1 ns
This IIR filter reads the input sample
from the memory location Y:input
and writes the filtered output sample
to the memory location Y:output
The samples are stored in the X memory
The coefficients are stored in the Y memory
The equations of the filter are:
Figure B 3 8 Pole 4 Multiply Cascaded Canonic IIR Filter (Sheet 1 of 2)
w(n)=
y(n)=
x(n)
rc
x(n)-ai1 * w(n-1)-ai2 * w(n-2)
w(n)+bi1 * w(n-1)+bi2 * w(n-2)
( - )
Freescale Semiconductor, Inc.
For More Information On This Product,
BENCHMARK PROGRAMS
BENCHMARK PROGRAMS
w(n)
ai1
ai2
June 30, 1988
Go to: www.freescale.com
z
z
-1
-1
w(n-2)
w(n-1)
bi1
bi2
( + )
y(n)
MOTOROLA