dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 564

• Manufacturer Part Number: dsp56000
• Description: 24-bit Digital Signal Processor Family Manual
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor, Inc.
INSTRUCTION TIMING
additional (if any) instruction program words that are required for the effective address of
the Jcc instruction. The term “jx’’ represents the number of additional (if any) oscillator
clock cycles required for a jump-type instruction.
2. Evaluate the “jx’’ term using Table A-11.
According to Table A-11, the Jcc instruction will require jx=ea+(2
ap) additional oscilla-
tor clock cycles. The term “ea’’ represents the number of additional (if any) oscillator
clock cycles that are required for the e ffective a ddressing mode specified in the Jcc
instruction. The term “ap’’ represents the number of additional (if any) oscillator clock
cycles that are required to a ccess a P memory operand. Note that the “+(2
ap)” term
represents the two program memory instruction fetches executed at the end of a one-
word jump instruction to refill the instruction pipeline.
3. Evaluate the “ea’’ term using Table A-13.
The JLC (R2+N2) instruction uses the “indexed by offset Nn” effective addressing mode.
According to Table A-13, this operation will require ea=0 additional instruction program
words and ea=2 additional oscillator clock cycles.
4. Evaluate the “ap’’ term using Table A-14.
According to Table A-14, the term “ap’’ depends upon where the referenced P memory
location is located in the DSP56K memory space. External memory accesses require
additional oscillator clock cycles according to the number of wait states programmed into
the DSP56K bus control register (BCR). Thus, assuming that the 16-bit bus control regis-
ter contains the value $2246, external P memory accesses require wp=4 w ait states or
additional oscillator clock cycles. For this example, the P memory reference is assumed
to be an external reference. Thus, according to Table A-14, the Jcc instruction will use
the value ap=wp=4 oscillator clock cycles.
5. Compute final results.
Thus, based upon the assumptions given for Table A-6 and those listed in the problem
statement for Example 2, the instruction
A - 298
INSTRUCTION SET DETAILS
MOTOROLA
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