dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 502

• Manufacturer Part Number: dsp56000
• Description: 24-bit Digital Signal Processor Family Manual
• Manufacturer: Freescale Semiconductor, Inc

Operation:
Description: Negate the destination operand D and store the result in the destination
accumulator. This is a 56-bit, twos-complement operation.
Example:
Explanation of Example: Prior to execution, the 56-bit B accumulator contains the
value $00:123456:789ABC. The NEG B instruction takes the twos complement of the
value in the B accumulator and stores the 56-bit result back in the B accumulator.
Condition Codes:
S — Computed according to the definition in A.5 CONDITION CODE COMPUTATION
L — Set if limiting (parallel move) or overflow has occurred in result
E — Set if the signed integer portion of A or B result is in use
U — Set if A or B result is unnormalized
N — Set if bit 55 of A or B result is set
Z — Set if A or B result equals zero
V — Set if overflow has occurred in A or B result
Note: The definitions of the E and U bits vary according to the scaling mode being used.
Refer to Section A.5 CONDITION CODE COMPUTATION for complete details.
A - 236
NEG
0–D
NEG B X1,X:(R3)+ Y:(R6)–,A
B
LF
1
5
D (parallel move)
:
:
DM
14
$00:123456:789ABC
Before Execution
13
T
Freescale Semiconductor, Inc.
**
12
For More Information On This Product,
MR
INSTRUCTION DESCRIPTIONS
S1
11
INSTRUCTION SET DETAILS
S0
10
Go to: www.freescale.com
Negate Accumulator
I1
9
I0
8
S
7
;0–B
Assembler Syntax:
B
L
6
NEG
E
5
B, update A,X1,R3,R6
$FF:EDCBA9:876544
After Execution
U
4
CCR
D (parallel move)
N
3
Z
2
V
1
C
0
MOTOROLA
NEG