dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 160

• Manufacturer Part Number: dsp56000
• Description: 24-bit Digital Signal Processor Family Manual
• Manufacturer: Freescale Semiconductor, Inc

7.5
The WAIT instruction brings the processor into the wait processing state which is one of
two low power-consumption states. Asserting the OnCE’s debug request pin releases
the DSP from the wait state. In the wait state, the internal clock is disabled from all inter-
nal circuitry except the internal peripherals. All internal processing is halted until an
unmasked interrupt occurs, the Debug Request pin of the OnCE is asserted, or the DSP
is reset.
Figure 7-15 shows a WAIT instruction being fetched, decoded, and executed. It is
fetched as n3 in this example and, during decode, is recognized as a WAIT instruction.
The following instruction (n4) is aborted, and the internal clock is disabled from all inter-
nal circuitry except the internal peripherals. The processor stays in this state until an
interrupt or reset is recognized. The response time is variable due to the timing of the
interrupt with respect to the internal clock. Figure 7-15 shows the result of a fast interrupt
bringing the processor out of the wait state. The two appropriate interrupt vectors are
fetched and put in the instruction pipe. The next instruction fetched is n4, which had been
aborted earlier. Instruction execution proceeds normally from this point.
Figure 7-16 shows an example of the WAIT instruction being executed at the same time
that an interrupt is pending. Instruction n4 is aborted as before. The WAIT instruction
causes a five-instruction-cycle delay from the time it is decoded, after which the interrupt
is processed normally. The internal clocks are not turned off, and the net effect is that of
executing eight NOP instructions between the execution of n2 and ii1.
7 - 36
i
ii
n = NORMAL INSTRUCTION WORD
= INTERRUPT
= INTERRUPT INSTRUCTION WORD
FETCH
DECODE
EXECUTE
INSTRUCTION CYCLE COUNT
WAIT PROCESSING STATE
INTERRUPT CONTROL CYCLE 1
INTERRUPT CONTROL CYCLE 2
Freescale Semiconductor, Inc.
Figure 7-15 Wait Instruction Timing
For More Information On This Product,
WAIT PROCESSING STATE
PROCESSING STATES
Go to: www.freescale.com
n2
n1
n3
1
WAIT
n4
n2
2
WAIT
—
—
3
4
ONLY INTERNAL PERIPHERALS
5
i
INTERRUPT SYNCHRONIZED AND
RECEIVE CLOCK
RECOGNIZED AS PENDING
6
i
ii1
7
ii2
ii1
8
n4
ii2
ii1
9
MOTOROLA
n5
n4
10
ii2