dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 349

• Manufacturer Part Number: dsp56000
• Description: 24-bit Digital Signal Processor Family Manual
• Manufacturer: Freescale Semiconductor, Inc

The DIV instruction calculates one quotient bit based on the divisor and the previous par-
tial remainder. To produce an N-bit quotient, the DIV instruction is executed N times
where N is the number of bits of precision desired in the quotient, 1 N 24. Thus, for a
full-precision (24 bit) quotient, 24 DIV iterations are required. In general, executing the
DIV instruction N times produces an N-bit quotient and a 48-bit remainder which has
(48–N) bits of precision and whose N MS bits are zeros. The partial remainder is not a
true remainder and must be corrected due to the nonrestoring nature of the division algo-
rithm before it may be used. Therefore, once the divide is complete, it is necessary to
reverse the last DIV operation and restore the remainder to obtain the true remainder.
The DIV instruction uses a nonrestoring fractional division algorithm which consists of
the following operations (see the previous Operation diagram):
MOTOROLA
DIV
1. Compare the source and destination operand sign bits: An exclusive OR
2. Shift the partial remainder and the quotient: The 55-bit destination accumu-
3. Calculate the next quotient bit and the new partial remainder: The 24-bit
operation is performed on bit 55 of the destination operand D and bit 23 of the
source operand S;
lator D is shifted one bit to the left. The carry bit C is moved into the LS bit (bit
0) of the accumulator;
source operand S (signed divisor) is either added to or subtracted from the
MSP portion of the destination accumulator (A1 or B1), and the result is stored
back into the MSP portion of that destination accumulator. If the result of the
exclusive OR operation previously described was a “1” (i.e., the sign bits were
different), the source operand S is added to the accumulator. If the result of
the exclusive OR operation was a “0” (i.e., the sign bits were the same), the
source operand S is subtracted from the accumulator. Due to the automatic
sign extension of the 24-bit signed divisor, the addition or subtraction opera-
tion correctly sets the carry bit C of the condition code register with the next
quotient bit.
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Divide Interation
DIV
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