dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 281
dsp56000
Manufacturer Part Number
dsp56000
Description
24-bit Digital Signal Processor Family Manual
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.DSP56000.pdf
(637 pages)
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A.5
The condition code register (CCR) portion of the status register (SR) consists of eight
defined bits:
The E, U, N, Z, V, and C bits are true condition code bits that reflect the condition of the
result of a data ALU operation . These condition code bits are not latched and are not
affected by address ALU calculations or by data transfers over the X, Y, or global
data buses. The L bit is a latching overflow bit which indicates that an overflow has
occurred in the data ALU or that data limiting has occurred when moving the contents of
the A and/or B accumulators. The S bit is a latching bit used in block floating point oper-
ations to indicate the need to scale the number in A or B. See SECTION 5 – PROGRAM
CONTROL UNIT for information on the MR portion of the status register.
The standard definition of the condition code bits follows. Exceptions to these stan-
dard definitions are given in the notes which follow Table A-5.
MOTOROLA
CONDITION CODE COMPUTATION
S — Scaling Bit
L — Limit Bit
E — Extension Bit
U — Unnormalized Bit
15
LF
DM
14
13
T
Freescale Semiconductor, Inc.
**
12
For More Information On This Product,
CONDITION CODE COMPUTATION
MR
S1
11
INSTRUCTION SET DETAILS
10
S0
Go to: www.freescale.com
I1
9
N — Negative Bit
Z — Zero Bit
V — Overflow Bit
C — Carry Bit
I0
8
7
S
6
L
5
E
U
4
CCR
N
3
2
Z
1
V
C
0
A - 15
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