dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 458

• Manufacturer Part Number: dsp56000
• Description: 24-bit Digital Signal Processor Family Manual
• Manufacturer: Freescale Semiconductor, Inc

Operation:
Class I
Class II
where ( . . . . . ) refers to any arithmetic or logical instruction which allows parallel moves.
Description: Class I: Move a one-word operand from an accumulator (S1) to an input
register (D1) and move another word operand from/to Y memory. All memory addressing
modes, including absolute addressing and 24-bit immediate data, may be used. The reg-
ister to register move (S1,D1) allows a data ALU accumulator to be moved to a data ALU
input register for use as a data ALU operand in the following instruction.
Class II: Move one-word operand from a data ALU accumulator to Y memory and one-
word operand from data ALU register Y0 to a data ALU accumulator. One effective
address is specified. All memory addressing modes, excluding long absolute addressing
and long immediate data, may be used. Class II move operations have been added to
the R:Y parallel move (and a similar feature has been added to the X:R parallel move) as
an added feature available in the first quarter of 1989.
For both Class I and Class II R:Y parallel data moves, if the arithmetic or logical opcode-
operand portion of the instruction specifies a given destination accumulator, that same
accumulator or portion of that accumulator may not be specified as a destination D2 in
the parallel data bus move operation. Thus, if the opcode-operand portion of the instruc-
tion specifies the 56-bit A accumulator as its destination, the parallel data bus move por-
tion of the instruction may not specify A0, A1, A2, or A as its destination D2. Similarly, if
the opcode-operand portion of the instruction specifies the 56-bit B accumulator as its
destination, the parallel data bus move portion of the instruction may not specify B0, B1,
B2, or B as its destination D2. That is, duplicate destinations are NOT allowed within the
same instruction.
A - 192
R:Y
( . . . . . ); S1 D1; Y:ea D2
( . . . . . ); S1 D1; S2 Y:ea
( . . . . . ); S1 D1; #xxxxxx D2
( . . . . . ); Y0
( . . . . . ); Y0 B; B Y:ea
A; A Y:ea
Freescale Semiconductor, Inc.
For More Information On This Product,
Register and Y Memory Data Move
INSTRUCTION DESCRIPTIONS
INSTRUCTION SET DETAILS
Go to: www.freescale.com
Assembler Syntax:
Class I
Class II
( . . . . . ) S1,D1 Y:ea,D2
( . . . . . ) S1,D1 S2,Y:ea
( . . . . . ) S1,D1 #xxxxxx,D2
( . . . . . ) Y0,A A,Y:ea
( . . . . . ) Y0,B B,Y:ea
MOTOROLA
R:Y