dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 47

• Manufacturer Part Number: dsp56000
• Description: 24-bit Digital Signal Processor Family Manual
• Manufacturer: Freescale Semiconductor, Inc

one instruction cycle. The ANDI instruction clears the DM mode bit, but, due to the
instruction execution pipeline, the Data ALU leaves the mode after one instruction cycle.
The double precision multiply algorithm uses the Y0 register at all stages. If the use of
the Data ALU is required in an interrupt service routine, Y0 should be saved together
with other Data ALU registers to be used, and should be restored before leaving the
interrupt routine.
If just single precision times double precision multiply is desired, two of the multiply oper-
ations may be deleted and replaced by suitable initialization and clearing of the accumu-
lator and Y0. Figure 3-12 shows the single precision times double precision algorithm.
Figure 3-13 shows a single precision times double precision multiply-accumulate algo-
rithm. First, the least significant parts of the double precision values are multiplied by the
single precision values and accumulated in the “Double Precision Multiply” mode. Then
the DM bit is cleared and the least significant part of the result is saved to memory. The
most significant parts of the double precision values are then multiplied by the single pre-
MOTOROLA
clr a
ori
move
mac
mac
move
andi
non-Data ALU operation
#$40,mr
x0,y1,a
y1,x1,a
a,l:(r0)+
#$bf,mr
DP3_DP2_DP1 = MSP1_LSP1 x SP
R0
R1
Figure 3-12 Single
DOUBLE PRECISION MULTIPLY MODE
Freescale Semiconductor, Inc.
For More Information On This Product,
#0,y0
x:(r1)+,x0
x:(r1)+,x1
a0,x:(r0)+
DATA ARITHMETIC LOGIC UNIT
MSP1
LSP1
Go to: www.freescale.com
DP3
DP1
X:
Double Multiply Algorithm
y:(r5)+,y1
DP2
SP
Y:
;clear a and y0
;enter DP mode
;load LSP1 and SP
;LSP1*SP
;load MSP1
;shifted(a)+
; SP*MSP1
;save DP1
;save DP3_DP2
;exit DP mode
;pipeline delay
R5
R0
a,
a,
3 - 17