dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 108

• Manufacturer Part Number: dsp56000
• Description: 24-bit Digital Signal Processor Family Manual
• Manufacturer: Freescale Semiconductor, Inc

Some address register indirect modes require an offset and a modifier register for use in
address calculations. These registers are implied by the address register specified in an
effective address in the instruction word. Each offset register (Nn) and each modifier reg-
ister (Mn) is assigned to an address register (Rn) having the same register number (n).
Thus, the assigned register triplets are R0;N0;M0, R1;N1;M1, R2;N2;M2, R3;N3;M3,
R4;N4;M4, R5;N5;M5, R6;N6;M6, and R7;N7;M7. Rn is used as the address register; Nn
is used to specify an optional offset; and Mn is used to specify the type of arithmetic used
to update the Rn.
The addressing modes are grouped into three categories: register direct, address register
indirect, and special. These addressing modes are described in the following paragraphs.
Refer to Table 6-1 for a summary of the addressing modes and allowed operand
references.
6.3.5.1
These effective addressing modes specify that the operand source or destination is one
of the data, control, or address registers in the programming model.
6.3.5.1.1
The operand is in one, two, or three data ALU register(s) as specified in a portion of the
data bus movement field in the instruction. Classified as a register reference, this address-
ing mode is also used to specify a control register operand for special instructions such
as OR immediate to control registers (ORI) and AND immediate to control registers
(ANDI).
6.3.5.1.2
Classified as a register reference, the operand is in one of the 24 address registers (Rn,
Nn, or Mn) specified by an effective address in the instruction.
Note: Due to instruction pipelining, if an address register (Mn, Nn, or Rn) is changed with
a MOVE instruction, the new contents will not be available for use as a pointer until the
second following instruction.
6.3.5.2
The address register indirect mode description is presented in SECTION 4 - ADDRESS
GENERATION UNIT.
6 - 14
Register Direct Modes
Address Register Indirect Modes
Data or Control Register Direct
Address Register Direct
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