dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 422

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dsp56000

Manufacturer Part Number
dsp56000
Description
24-bit Digital Signal Processor Family Manual
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Instruction Fields 1:
Note: Only the indicated S1 S2 combinations are valid. X1 X1 and Y1 Y1 are not valid.
Timing: 2+mv oscillator clock cycles
Memory: 1+mv program words
Example 2:
Explanation of Example 2 : The content of Y0 ($654321) is negated, multiplied by 2
added to the content of the B accumulator ($00:100000:000000), placed in the B accu-
mulator and then rounded to a single precision number (24 bits in B1). The net effect of
this operation is to negate the content of Y0, divide the result by 2
to the accumulator. An alternate interpretation is that Y0 is negated, right shifted 10
places, filled with the sign bit (0 for a positive number and 1 for a negative number), the
result is added to the accumulator and then rounded to a single precision number.
A - 156
MACR
MACR -Y0,
S1 S2
X0 X0
Y0 Y0
X1 X0
Y1 Y0
X0 Y1
Y0 X0
X1 Y0
Y1 X1
Y0
B
:
:
Q Q Q
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
#10, B
$00:100000:000000
Before Execution
Freescale Semiconductor, Inc.
Signed Multiply-Accumulate and Round
For More Information On This Product,
$654321
INSTRUCTION DESCRIPTIONS
INSTRUCTION SET DETAILS
Go to: www.freescale.com
Sign
+
;
k
0
1
Y0
B
D d
A 0
B 1
$00:0FE6AF:000000
After Execution
$654321
10
and add the result
MACR
MOTOROLA
-10
,

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