dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 63
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dsp56000
Manufacturer Part Number
dsp56000
Description
24-bit Digital Signal Processor Family Manual
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.DSP56000.pdf
(637 pages)
- Current page: 63 of 637
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an extra instruction cycle, cannot be used for making XY: memory references.
4.4.1.7
The address of the operand is the contents of the address register, Rn, decremented by
1 before the operand address is used (see Table 4-1 and Figure 4-10). The contents of
Rn are decremented and stored in the same address register. This addressing mode re-
quires an extra instruction cycle. This mode cannot be used for making XY: memory
references, nor can it be used for modifying the contents of Rn without an associated data
MOTOROLA
EXAMPLE: MOVE X1,X: (R2)+N2
Assembler Syntax: (Rn)+Nn
Memory Spaces: P:, X:, Y:, XY:, L:
Additional Instruction Execution Time (Clocks): 0
Additional Effective Address Words: 0
47
23
A
Figure 4-7 Address Register Indirect — Postincrement by Offset Nn
5
Predecrement By 1
B 4
X1
BEFORE EXECUTION
$3204
$3200
C
24 23
6
0 23
23
X X X X X X
X X X X X X
Freescale Semiconductor, Inc.
0 0
M2
R2
N2
X MEMORY
For More Information On This Product,
15
15
15
ADDRESS GENERATION UNIT
0
X0
$3200
$0004
$FFFF
0
Go to: www.freescale.com
0
1
0
0
0
0
0
0
ADDRESSING
47
23
A
5
B
X1
AFTER EXECUTION
4
$3204
$3200
C
24 23
6
0 23
23
X X X X X X
$ A 5 B 4 C 6
0
M2
R2
N2
X MEMORY
0
15
15
15
X0
0
$3204
$0004
$FFFF
0
0
0
1
0
0
0
0
0
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