dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 184

• Manufacturer Part Number: dsp56000
• Description: 24-bit Digital Signal Processor Family Manual
• Manufacturer: Freescale Semiconductor, Inc

cleared. To enable rapid recovery when exiting the STOP state, at the cost of higher
power consumption in the STOP state, PSTP should be set. PSTP is cleared by hard-
ware reset.
9.2.5.5 PCTL PLL Enable Bit (PEN) - Bit 18
The PEN bit enables the PLL operation. When this bit is set, the PLL is enabled and the
internal clocks will be derived from the PLL VCO output. When this bit is cleared, the PLL
is disabled and the internal clocks are derived directly from the clock connected to the
EXTAL pin. When the PLL is disabled, the VCO does not operate in order to minimize
power consumption. The PLOCK pin is asserted when PEN is cleared. The PEN bit may
be set by software but it cannot be reset by software. During hardware reset this bit
receives the value of the PINIT pin. The only way to clear PEN is to hold the PINIT pin
low during hardware reset.
A relationship exists between PSTP and PEN where PEN adjusts PSTP’s control of the
PLL operation. When PSTP is set and PEN (see Table 9-3) is cleared, the on-chip crys-
tal oscillator remains operating in the STOP state, but the PLL is disabled. This power
saving feature enables rapid recovery from the STOP state when the user operates the
chip with an on-chip oscillator and with the PLL disabled.
9.2.5.6 PCTL Clock Output Disable Bits (COD0-COD1) - Bits 19-20
The COD0-COD1 bits control the output buffer of the clock at the CKOUT pin. Table 9-4
specifies the effect of COD0-COD1 on the CKOUT pin. When both COD0 and COD1 are
set, the CKOUT pin is held in the high (“1”) state. If the CKOUT pin is not connected to
external circuits, it is recommended that both COD1 and COD0 be set (disabling clock
output) to minimize RFI noise and power dissipation. If the CKOUT output is low at the
moment the COD0-COD1 bits are set, it will complete the low cycle and then be disabled
high. If the programmer re-enables the CKOUT output before it reaches the high logic
level during the disabling process, the CKOUT operation will be unaffected. The
COD0-COD1 bits are cleared by hardware reset.
9 - 8
PSTP
0
1
1
PEN
0
1
x
Freescale Semiconductor, Inc.
Table 9-3 PSTP and PEN Relationship
For More Information On This Product,
Operation during STOP
Disabled
Disabled
Enabled
PLL
PLL CLOCK OSCILLATOR
Go to: www.freescale.com
PLL COMPONENTS
Oscillator
Disabled
Enabled
Enabled
Recovery
rapid
rapid
long
Power Consumption
minimal
higher
lower
MOTOROLA