dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 196

• Manufacturer Part Number: dsp56000
• Description: 24-bit Digital Signal Processor Family Manual
• Manufacturer: Freescale Semiconductor, Inc

10.2.4 Debug Request Input (DR)
The debug request input (DR) allows the user to enter the debug mode of operation from
the external command controller. When DR is asserted, it causes the DSP56K to finish
the current instruction being executed, save the instruction pipeline information, enter the
debug mode, and wait for commands to be entered from the DSI line. While in debug
mode, the DR pin lets the user reset the OnCE controller by asserting it and deasserting
it after receiving acknowledge. It may be necessary to reset the OnCE controller in cases
where synchronization between the OnCE controller and external circuitry is lost. DR
must be deasserted after the OnCE responds with an acknowledge on the DSO pin and
before sending the first OnCE command. Asserting DR will cause the chip to exit the
STOP or WAIT state.
10.3
The OnCE Controller and Serial Interface contains the following blocks: OnCE command
register, bit counter, OnCE decoder, and the status/control register. Figure 10-3 illustrates
a block diagram of the OnCE controller and serial interface
10.3.1 OnCE Command Register (OCR)
The OCR is an 8-bit shift register that receives its serial data from the DSI pin. It holds the
8-bit commands to be used as input for the OnCE Decoder. The Command Register is
shown in Figure 10-4.
MOTOROLA
ISTRACE
ISDR
OnCE CONTROLLER AND SERIAL INTERFACE
ISBKPT
ISSWDBG
ISDEBUG
OnCE CONTROLLER AND SERIAL INTERFACE
Figure 10-3 OnCE Controller and Serial Interface
Freescale Semiconductor, Inc.
For More Information On This Product,
REG READ
ON-CHIP EMULATION (OnCE)
.
OnCE COMMAND REGISTER
OnCE DECODER
Go to: www.freescale.com
REG WRITE
.
BIT 23
BIT 7
STATUS AND CONTROL
MODE SELECT
REGISTER
BIT COUNTER
.
.
.
DSI
DSCK
DSO
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