dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 567

• Manufacturer Part Number: dsp56000
• Description: 24-bit Digital Signal Processor Family Manual
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
Note 1: The STOP instruction disables the internal clock oscillator. After clock turn on, an internal counter counts
Note 2: The WAIT instruction takes a minimum of 16 cycles to execute when an internal interrupt is pending
Note 3: If assumption 4 is not applicable, then to each one-word instruction timing, a “+ap” term should be
Mnemonic
ABS
ADC
ADD
ADDL
ADDR
AND
ANDI
ASL
ASR
BCHG
BCLR
BSET
BTST
CLR
CMP
CMPM
DEBUG
DEBUGcc
DEC
DIV
DO
ENDDO
EOR
INC
Jcc
JCLR
JMP
JScc
JSCLR
JSET
JSR
JSSET
LSL
65,536 clock cycles (if bit 6 in the OMR is clear) before enabling the clock to the internal DSP circuits. If
bit 6 in the OMR is set, only six clock cycles are counted before enabling the clock to the external
DSP circuits.
during the execution of the WAIT instruction.
added, and, to each two-word instruction, a “+(2*ap)” term should be added to account for the program
memory wait states spent to fetch an instruction word to fill the pipeline.
Instruction
Table A-6 Instruction Timing Summary (see Note 3)
Program
Words
1 + mv
1 + mv
1 + mv
1 + mv
1 + mv
1 + mv
1 + mv
1 + mv
1 + mv
1 + mv
1 + mv
1 + mv
1 + mv
1 + ea
1 + ea
1 + ea
1 + ea
1 + ea
1 + ea
1 + ea
1 + ea
1
1
1
1
1
2
1
1
2
2
2
2
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4 + mvb
4 + mvb
4 + mvb
4 + mvb
Cycles
2 + mv
2 + mv
2 + mv
2 + mv
2 + mv
2 + mv
2 + mv
2 + mv
2 + mv
2 + mv
2 + mv
6 + mv
2 + mv
2 + mv
Clock
4 + jx
6 + jx
4 + jx
4 + jx
6 + jx
6 + jx
4 + jx
6 + jx
Osc.
INSTRUCTION SET DETAILS
2
4
4
2
2
2
2
INSTRUCTION TIMING
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Notes
LSR
LUA
MAC
MACR
MOVE
MOVEC
MOVEM
MOVEP
MPY
MPYR
NEG
NOP
NORM
NOT
OR
ORI
REP
RESET
RND
ROL
ROR
RTI
RTS
SBC
STOP
SUB
SUBL
SUBR
SWI
Tcc
TFR
TST
WAIT
Mnemonic
Instruction
Program
Words
1 + mv
1 + mv
1 + mv
1 + mv
1 + mv
1 + mv
1 + mv
1 + mv
1 + mv
1 + mv
1 + mv
1 + mv
1 + mv
1 + mv
1 + mv
1 + mv
1 + mv
1 + mv
1 + ea
1 + ea
1 + ea
1
1
1
1
1
1
1
1
1
1
1
1
6 + ea + ap
2 + mvc
2 + mvp
Cycles
2 + mv
2 + mv
2 + mv
2 + mv
2 + mv
2 + mv
2 + mv
2 + mv
2 + mv
4 + mv
2 + mv
2 + mv
2 + mv
2 + mv
2 + mv
2 + mv
2 + mv
2 + mv
2 + mv
Clock
4 + rx
4 + rx
Osc.
n/a
n/a
4
2
2
2
4
8
2
Notes
1
2
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