dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 35
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dsp56000
Manufacturer Part Number
dsp56000
Description
24-bit Digital Signal Processor Family Manual
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.DSP56000.pdf
(637 pages)
- Current page: 35 of 637
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3.2.1 Data ALU Input Registers (X1, X0, Y1, Y0)
X1, X0, Y1, and Y0 are four 24-bit, general-purpose data registers. They can be treated
as four independent, 24-bit registers or as two 48-bit registers called X and Y, developed
by concatenating X1:X0 and Y1:Y0, respectively. X1 is the most significant word in X and
Y1 is the most significant word in Y. The registers serve as input buffer registers between
the XDB or YDB and the MAC unit. They act as Data ALU source operands and allow
new operands to be loaded for the next instruction while the current instruction uses the
MOTOROLA
OVERVIEW AND DATA ALU ARCHITECTURE
X DATA BUS
Y DATA BUS
SHIFTER
Freescale Semiconductor, Inc.
56
For More Information On This Product,
DATA ARITHMETIC LOGIC UNIT
Go to: www.freescale.com
Figure 3-2 Data ALU
SHIFTER/LIMITER
AND LOGIC UNIT
ACCUMULATOR,
MULTIPLIER
ROUNDING,
24
24
56
X0
X1
Y0
Y1
A (56)
B (56)
56
56
24
24
24
24
56
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