dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 452

• Manufacturer Part Number: dsp56000
• Description: 24-bit Digital Signal Processor Family Manual
• Manufacturer: Freescale Semiconductor, Inc

Operation:
where ( . . . . . ) refers to any arithmetic or logical instruction which allows parallel moves.
Description: Move the specified word operand from/to Y memory. All memory address-
ing modes, including absolute addressing and 24-bit immediate data, may be used.
Absolute short addressing may also be used.
If the arithmetic or logical opcode-operand portion of the instruction specifies a given
destination accumulator, that same accumulator or portion of that accumulator may not
be specified as a destination D in the parallel data bus move operation. Thus, if the
opcode-operand portion of the instruction specifies the 56-bit A accumulator as its desti-
nation, the parallel data bus move portion of the instruction may not specify A0, A1, A2,
or A as its destination D. Similarly, if the opcode-operand portion of the instruction speci-
fies the 56-bit B accumulator as its destination, the parallel data bus move portion of the
instruction may not specify B0, B1, B2, or B as its destination D. That is, duplicate des-
tinations are NOT allowed within the same instruction.
If the opcode-operand portion of the instruction specifies a given source or destination
register, that same register or portion of that register may be used as a source S in the
parallel data bus move operation. This allows data to be moved in the same instruction in
which it is being used as a source operand by a data ALU operation. That is, duplicate
sources are allowed within the same instruction.
When a 24-bit source operand is moved into a 16-bit destination register, the 16 LS bits
of the 12-bit source operand are stored in the 16-bit destination register. When a 16-bit
source operand is moved into a 24-bit destination register, the 16 LS bits of the destina-
tion register are loaded with the contents of the 16-bit source operand, and the eight MS
bits of the 24-bit destination register are zeroed.
A - 186
Y:
( . . . . . ); Y:ea D
( . . . . . ); Y:aa D
( . . . . . ); S Y:ea
( . . . . . ); S Y:aa
( . . . . . ); #xxxxxx D
Freescale Semiconductor, Inc.
For More Information On This Product,
INSTRUCTION DESCRIPTIONS
INSTRUCTION SET DETAILS
Y Memory Data Move
Go to: www.freescale.com
Assembler Syntax:
( . . . . . ) Y:ea,D
( . . . . . ) Y:aa,D
( . . . . . ) S,Y:ea
( . . . . . ) S,Y:aa
( . . . . . ) #xxxxxx,D
MOTOROLA
Y: