dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 569

• Manufacturer Part Number: dsp56000
• Description: 24-bit Digital Signal Processor Family Manual
• Manufacturer: Freescale Semiconductor, Inc

Note that the “ap” term in Table A-8 and Table A-9 for the P memory move represents
the wait states spent when accessing the program memory during DATA read or write
operations and does not refer to instruction fetches.
All one-word jump instructions execute TWO program memory fetches to refill the pipe-
line, which is represented by the “+(2
All two-word jumps execute THREE program memory fetches to refill the pipeline, but
one of those fetches is sequential (the instruction word located at the jump instruction
2nd word address+1), so it is not counted as per assumption 4. If the jump instruction
was fetched from a program memory segment with wait states, another “ap’’ should be
added to account for that third fetch.
MOTOROLA
Table A-10 Bit Manipulation Timing Summary (see Note 2)
Note 1: Jbit = JCLR, JSCLR, JSET, and JSSET
Note 2: Jxxx = Jcc, JMP , JScc, and JSR
Jbit Register Direct
Jbit Peripheral
Jbit X Memory
Jbit Y Memory
Jxxx
Note 1: Bxxx = BCHG, BCLR, or BSET.
Note 2: If assumption 4 is not applicable, then to each one-word instruction timing,
Jump Instruction Operation
Bxxx Periphera l
Bxxx X Memory
Bxxx Y Memory
Bxxx Register Direct
BTST Peripheral
BTST X Memory
BTST Y Memory
Table A-11 Jump Instruction Timing Summary
Bit Manipulation Operation
a “+ ap” term should be added, and to each two-word instruction, a “+ (2 * ap)”
term should be added to account for the program memory wait states spent to
fetch an instruction word to fill the pipeline.
Freescale Semiconductor, Inc.
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INSTRUCTION TIMING
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ap)” term.
ea + ax + (2
ea + ay + (2
aio + (2
ea + (2
ea + (2
ea + (2
ea + ax
ea + ay
Cycles
2
Cycles
+ mvb
2
+ jx
aio
0
aio
ap
ax)
ay)
ap)
ap)
ap)
ap)
Comments
See Note 1
See Note 1
See Note 1
See Note 1
Comments
See Note 1
See Note 1
See Note 1
See Note 1
See Note 2
A - 303