dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 395

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dsp56000

Manufacturer Part Number
dsp56000
Description
24-bit Digital Signal Processor Family Manual
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Notes: If A or B is specified as the destination operand, the following sequence of events
Timing: 6+jx oscillator clock cycles
Memory: 2 program words
MOTOROLA
JSCLR
1. The S bit is computed according to its definition (See Section A.5)
2. The accumulator value is scaled according to the scaling mode bits S0
3. If the accumulator extension is in use, the output of the shifter is limited to
4. The bit test is performed on the resulting 24-bit value, and the jump to sub-
takes place:
and S1 in the status register (SR).
the maximum positive or negative saturation constant, and the L bit is set.
routine is taken if the bit tested is clear. The original contents of A or B are
not changed.
Freescale Semiconductor, Inc.
For More Information On This Product,
Jump to Subroutine if Bit Clear
INSTRUCTION DESCRIPTIONS
INSTRUCTION SET DETAILS
Go to: www.freescale.com
JSCLR
A - 129

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